The integrity of information stored in computer memory cannot be guaranteed. Bits stored for instance in computer memory such as dynamic random access memory (DRAM) are susceptible to fault events due to unintended change of electric values and/or characteristics representing the stored bits. Such unintended value change may be categorized into “hard” errors, which are permanent errors, in particular errors caused by hardware defects, or “soft” errors, which are non-permanent errors, in particular errors caused by electromagnetic and/or particle radiation, such as cosmic radiation or radiation from decay of radioactive material. Soft errors are unpredictable and occur in memory at random locations and times, although at an average rate, which can be empirically determined.
A scheme for detecting and correcting errors in computer memory involves storing, in addition to the data to be protected against errors, an error correction code (“ECC”) in association with the data. A number of algorithms are available for generating error correction codes, which permit the detection or correction of one or more bit errors in the bit sequence of data.
In general, an error correction (“EC”) scheme can be devised to detect or correct a one-bit error in each EC cycle using an ECC with a given bit length. In order to detect or correct two or more errors per EC cycle, an ECC with a larger number of bits is needs. For instance, so-called Hamming codes are used, which provide single bit error correction and double bit error detection (SEC-DED).
Today's dynamic random access memory (DRAM) technology is largely dominated by the JEDEC memory standards for computer memory (RAM) of the JEDEC Solid State Technology Association. In particular, the JEDEC memory standards include the Double data rate synchronous dynamic random-access memory (DDR SDRAM) standard, the latest version of which is version 4 generally denoted as DDR4.
The JEDEC's DDR standards include specifications of ECC blocks, which comprise encoder/decoder-correlators to detect and correct single-bit errors and to detect double-bit errors (e.g. using 8-bit ECC for each 64-bit data). The ECC block of the JEDEC's DDR standards address primarily the fields of servers such as file server, multi-user application server, scientific and financial application servers etc. The implementation of ECC DDR RAM modules requires additional wiring for the 8-bit ECC, which is economically unacceptable in embedded cost sensitive applications, and further raises the power requirement, which is also unacceptable in embedded low-power applications. Moreover, it should be noted that the ECC blocks specified according to the JEDEC's DDR standards do not meet the requirements of functional safety (e.g. as per ISO 26262) required for embedded applications in safety critical application use cases.
The low power implementations of the JEDEC DDR standards in turn address primarily mobile consumer devices such as mobile phones, tablets, notebooks and the like. The low power implementations of the JEDEC DDR standards lack a specifications of ECC blocks since the addressed fields of usage lack the error correction requirement. However, an increasing number of embedded applications make use of such low power implementations, e.g. according to JEDEC's LPDDR specifications, for meeting power constraints. In particular, embedded applications in the field of transportation have to meet the requirements of safety critical systems (e.g. as per ISO 26262).
Hence, there is a need to provide an economic and bandwidth efficient error detection and/or error correction scheme for memory controllers with selective data protections schemes adapted to different constraints and requirements supporting e.g. non-ECC random access memory (RAM), in particular low power non-ECC random access memory (RAM).